The 2.5 GHz pipelined HotPipe processor has an ideal CPU CPI of 1 when there are no misses. 2. Computer Architecture Objective type Questions and Answers.
The solutions given assume the base CPI = 1.4 throughput. Since the question is am-biguous, you could assume pipelining changes the CPI to 1. CPI for pipelined shall be the maximum time latency relative to all the stages in the pipeline Stalls per instruction = 0.2 × 1 cycle + 0.05 × 2 cycle = 0.3. Hence, we can compute the pipelined CPI: CPI pipelined = Ideal CPI + Pipeline stall clock cycles per instruction = 1 + Pipeline stall clock cycles per instruction If we ignore the cycle time overhead of pipelining and assume the stages are per- fectly balanced, then the cycle time of the two processors can be equal, leading to Pipeline depth 1 + Pipeline … pipeline speedup = ideal CPI x Pipeline depth / (ideal CPI +stall) Register Forwarding To reduce stall caused by data hazard, use register forwarding (or bypass) to handle RAW. Pipeline stalls are introduced in the pipelines architecture, so CPI will increase. Pipelining typically reduces the processor's cycle time and increases the throughput of instructions. (a) The clock period for the pipelined processor is decided by the longest pipeline stage (1.75 ns for the EX stage) Pipeline register delay = 0.25 ns Therefore: Clock period for pipelined processor = 1.75 + 0.25 = 2 ns Clock rate = 1 / Clock period = 0.5 GHz (b) Ideal CPI = 1 The processor needs to incur a 2-cycle stall after every 6 instructions. Please see Set 1 for Execution, Stages and Performance (Throughput) and Set 2 for Dependencies and Data Hazard. Hence, the pipelined CPI is CPI pipelined = Ideal CPI + Pipeline stall clock cycles per instruction = 1 + Pipeline stall clock cycles per instruction If we ignore the cycle time overhead of pipelining and assume the stages are all perfectly balanced, then the cycle time of the two machines are equal and CPI … In uniform delay pipeline, Cycle Time (Tp) = Stage Delay If buffers are included between the stages then, Cycle Time (Tp) = Stage Delay + Buffer Delay How to improve (decrease) CPI •Recall: CPI = Ideal CPI + CPI contributed by stalls •Ideal CPI =1 for single issue machine even with multiple execution units •Ideal CPI will be less than 1 if we have several execution units and we can issue (and “commit”) multiple instructions in …
The speed up achieved in this pipelined processor is-3.2; 3.0; 2.2; 2.0 . Types of pipeline. Assume there are no stalls in the pipeline. New CPI = old CPI + stalls per cycle = 1.4 + 0.3 = 1.7. so, Pipelined architecture will have CPI of 1.7. The ideal CPI on a pipelined processor is almost always 1. CPI for non pipelined processors = which is basically summation of all the time latency faced during each instruction while ignoring delays due to other buffers/latches/registers, CPI = 2+1.5+2+3+1 = 9.5 2.)
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